Many circuits and complex, multi-staged electronic systems that previously were regarded as economically unfeasible and practical, are now realizable using integrated circuits. The fabrication of a single-crystal monolithic circuit involves the formation of diodes, transistors, resisters and capacitors on a single microelectronic substrate. In practice, a microelectronic substrate for a semi-conductor IC's is formed on a silicon wafer, the patterns for circuit processing being applied to the wafer by photolithography. Each wafer contains the patterns of many identical integrated circuits. After the patterns are tested, the wafer is sliced into "dice," each die containing a single circuit.
In an integrated circuit pattern, the input, output, power supply and other terminals of the circuit are formed by metalized contacts, usually deployed along the periphery or margins of the pattern. The outline of the pattern is either square or rectangular, and the marginal locations of the contacts thereon depend on the circuit configuration and the available marginal space. Thus, in a relatively simple circuit pattern, all of the marginal space may be available for contacts, whereas in more complex circuits, portions of the circuit may invade the marginal areas so that contact placement is restricted to the free marginal areas. In some instances, therefore, the contacts may lie in more or less uniform rows along the margins, and in other cases, the contacts may be randomly spaced from each other.
Immediately following manufacture of the IC, the electrical characteristics of the device must be tested using a test probe assembly which includes a test probe card consisting of a printed circuit board having an opening therein to provide access to an IC pattern. The opening is surrounded by a ring of conductive pads connected by the printed circuit to card terminals for connection to test equipment appropriate for testing the circuit. The number of pads in the ring determines the maximum capicity of the probe card.
A higher degree of integration in recent semi-conductor devices has led to an increase in the number of electrodes in ICs, and to a decrease in the size of the electrode pads which are contacted by the probe needles. The reduction in size and increase in density of the probe needles has inevitably made the manufacture and mounting of the needles on the probe card troublesome. The tips of the probe needles are ideally all disposed at the same height level and same angle, but these, and other parameters of the needles fluctuate somewhat for a number of reasons. These variations in probe needle parameters reduce test precision and reliability. The following U.S. Patents disclose various probe card arrangements, as well as various techniques and methods for assuring proper alignment of the probe tip needles:
U.S. Pat. No. Issue Date 4,780,836 October 25, 1988 5,061,894 October 29, 1991 5,642,056 June 24, 1997 5,631,573 May 20, 1997 5,521,518 May 28, 1996
As will be discussed later in more detail, the effectiveness, reliability and repeatability of IC testing using a probe card depends on a number of factors and characteristics of the probe card, and particularly the probe needles, including size, alignment, leakage, contact resistance and the force applied by the needles. All of these factors are influenced to some degree by the angle of the probe tip. According to current industry standards, the ideal angle of the probe tip should be between 103 and 107 degrees, which will typically result in the application of a force between 1.5 and 2 grams per mil, when 3 mils of overtravel is provided. In the past, apparatus and methods have been devised for measuring the tip angle before the probe is assembled but no methods have been available for measuring tip angle after the probe card is assembled. Even after the probe card is assembled, the tip angle of one of more of the probe needles may be inadvertently altered during the sometimes complex set up of the test probe assembly. In those cases where tip angle has been altered so as to be out of tolerance, the out of tolerance probe needle may fail to make proper contact with a conductor pad on the IC, thus providing false or inaccurate testing, which in turn reduces production yield. In other cases, an out of tolerance probe tip angle may result in the application of too much or too little force on the conductor pad, which in turn results in over or under scrubbing of the pad. Where the pad is underscrubbed by the needle tip, no probe mark may be left on the pad, whereas too great a probe force results in a damaged bond pad.
Accordingly, there is a need in the art for a method of assuring proper probe tip angle on a probe card after the card is assembled, as well as a method for measuring the probe tip angle.